1. Technical Field
The invention is related to clock recovery circuits for multi-Gigabit digital communication system, and in particular to oscillators used by such clock recovery circuits.
2. Background Art
A receiver in a digital communication system employs a clock recovery circuit to reconstruct the clock signal embedded in the received signal. The receiver uses a control loop to maintain frequency and phase lock with the embedded clock signal. Some clock recovery systems use the output of a local oscillator that is not locked to the embedded clock in order to create the recovered clock signal. Such a clock recovery system operates in a feedback loop that is independent of the local oscillator. The local oscillator is neither frequency nor phase locked to the embedded clock signal, so that the phase of the local oscillator constantly rotates relative to the embedded clock signal. The rate at which the phase rotates is proportional to the difference between the received signal""s embedded clock signal and the frequency of the local oscillator. The frequency difference is compensated by the clock recovery system rotating the phase of the local oscillator output accordingly, so as to maintain frequency lock. For this purpose, the local oscillator can be a multi-stage ring oscillator, i.e., having n stages. The rotation of the phase of its output is performed by selecting successively different oscillator stages as the output.
In multi-Gigabit digital communications, the frequencies are so high that the cost of components such as a multi-GigaHertz local oscillator can be prohibitively high. It is not practical to make a multi-GigaHertz local oscillator using ordinary Silicon integrated circuit structures and processes, and far more expensive structures and processes, such as Germanium, must be employed. One way around this might be to use successive stages of a multi-stage local oscillator as successive phases of the recovered clock signal. For example, if the embedded clock in the received signal is 25 Gigabits/second, and if the local oscillator is a ring oscillator having 10 stages, then the local oscillator could be designed to run at 2.5 Gigabits/second and each of the 10 stages would output the leading edge of a corresponding one of 10 successive phases of a 25 Gigabit/second clock signal. The advantage here is that a 2.5 Gigabit/second oscillator can be fabricated in standard Silicon processes and therefore can be very inexpensive.
This would be only a partial solution: No provision has been made to rotate the phase of the local oscillator output to maintain frequency lock with the received signal""s embedded clock. This is because there are no spare local oscillator stages, each stage being used to provide one of ten phases of the recovered clock signal. In the foregoing example, spare stages could be provided by quintupling the number of stages (i.e., so that there are now 50 stages of the local oscillator). In this case, each of the ten phases of the clock signal would be derived from every fifth local oscillator stage, and the phase may be rotated in increments of one-fifth of the clock period. Even this is only a partial solution, because incrementing (or decrementing) the local oscillator output phase by one-fifth of the clock period involves such a large change that it induces jitter in the clock signal, which can disrupt communication. In order to reduce such jitter or phase noise, the xe2x80x9cphase resolutionxe2x80x9d of the local oscillator must be increased by increasing the number of stages of the local oscillator even further. In the foregoing example, the number of local oscillator stages can be increased to one hundred, so that the ten phases of the recovered clock signal would be derived from every tenth local oscillator stage, and the phase could be rotated in increments of one-tenth of the clock period. This would reduce the jitter, and even better reductions in jitter could be attained by ever expanding numbers of local oscillator stages. For example, very fine phase resolution could be obtained by using a local oscillator having a thousand stages. In the foregoing example, a one-thousand stage oscillator would mean that each of the ten phases of the recovered clock would be derived from every one hundred stages, and the phase would be rotated in increments of one-hundredth of a clock period. However, at this point the cost of the oscillator will have far exceeded any practical commercial limits, and the physics of semiconductors limits the number of ring oscillator stages possible for a given oscillator frequency.
Thus, it has seemed that digital communication systems operating at multi-Gigabit/second rates must necessarily involve a compromise between cost and performance, the cost being entailed in the number of local ring oscillator stages and the performance being limited by the clock jitter that worsens as the number of stages is reduced. It would be desirable to achieve optimum performance (e.g., achieving unlimited phase resolution in the local oscillator) without increasing cost (e.g., without having to increase the number of oscillator stages) while permitting the oscillator to run at least an order of magnitude below the embedded clock signal rate.
In a high speed digital communication receiver, an oscillator of oscillator frequency f has a plurality of n stages connected serially having a delay of 1/(nxc3x97f) between successive stages. A plurality of n variable analog delays are connected to respective ones of the n stages, outputs of the n variable analog delays providing n successive cycles of a clock signal of frequency nxc3x97f. A delay control circuit varies the delay interposed by each of the variable delays through a range of 1/(nxc3x97f). The apparatus delay control circuit can vary the delay in m equal steps, whereby the oscillator exhibits nxc3x97m virtual oscillator stages, so that the oscillator provides a phase resolution of 1/(mxc3x97nxc3x97f). A series-to-parallel converter has a first set of inputs to which outputs of the variable analog delays are connected and a second input to which a received signal is connected. A clock recovery circuit responds to an embedded clock signal within the received signal to control the delay control circuit so as to frequency-lock the outputs of the variable analog delays to the embedded clock signal. A phase comparator has a pair of inputs and an output connected to the delay control circuit, one of the phase comparator inputs being connected to an output of a selected one of the variable analog delays and the other of the phase comparator inputs being connected to one of the oscillator stages. The delay control circuit is programmed to return each of the variable analog delays to an initial delay value after the phase of the output of each variable analog delay reaches the phase of an adjacent oscillator stage, as sensed by the comparator.